1. Field of the Invention
The present invention relates to a static random-access memory (SRAM), especially to a write operation of the SRAM.
2. Description of the Prior Art
FIG. 1 illustrates a circuit of a memory cell of an SRAM. The memory cell 110 includes 6 transistors, where the transistor 112 and the transistor 114 form an inverter, and the transistor 122 and the transistor 124 form another inverter. An output of one of the two inverters is connected to an input of the other inverter so a latch that stores one bit data is formed. These two inverters are coupled to a pair of bit lines 132 and 134 through the transistor 116 and the transistor 126, respectively. The transistor 116 and the transistor 126 are coupled to the word line 140. By controlling the on/off states of the transistor 116 and the transistor 126 via the word line 140, access to the memory cell 110 can be manipulated.
When the memory cell 110 stores a binary data of 1 (supposing that an output Q of one of the two inverters is at a logic high level whereas an output QB of the other inverter is at a logic low level) and a binary data of 0 is about to be written to the memory cell 110, the bit line 132 is at the logic low level whereas the bit line 134 is at the logic high level. When the transistor 116 is on, there is a current flowing through the transistor 112 and the transistor 116 and pulling down the voltage level at the output Q. FIGS. 2A and 2B show voltage variations at the outputs of the inverters during a write operation of the memory cell 110. As shown in FIG. 2A, the transistor 116 and the transistor 126 are on in the interval TWL when the word line is asserted (being at the logic high level). The voltage level at the output Q decreases due to discharge whereas the voltage level at the output QB increases. When the interval TWL is over (the word line being at the logic low level again), the voltage level at the output Q becomes low and the voltage level at the output QB becomes high, which means that the write operation succeeds and therefore the binary data stored in the memory cell 110 changes from 1 to 0. If, however, the discharge current is not great enough, or the pull-up strength of the transistor 112 is too high, the voltage level at the output Q is not able to change from the logic high level to the logic low level in the interval TWL, and the voltage level at the output QB is not able to change correspondingly from the logic low level to the logic high level, which means the write operation fails, as shown in FIG. 2B.